Huawei Accelerates Its AI Chip Roadmap With Ascend 960 as AI Infrastructure Race Intensifies

Huawei is moving faster on its next AI chips

The AI hardware race is getting another major update.

At HUAWEI CONNECT 2026 in Shanghai, Huawei announced that it is bringing forward parts of its next-generation Ascend AI accelerator roadmap. The company says the training-focused Ascend 960DT will be available in the first quarter of 2027, three quarters earlier than its previous roadmap. A second chip, the inference-focused Ascend 960PR, is planned for the third quarter of 2027.

Huawei also laid out plans for the Ascend 970 in 2028 and Ascend 980 in 2029.

The announcement is important because AI infrastructure is increasingly becoming a systems problem rather than a single-chip problem. Training and running large AI models requires enormous amounts of computing power, memory and data movement. Huawei is trying to address all three through its chip roadmap and a broader architecture built around SuperPoDs, UnifiedBus and optical interconnect technology.

What Huawei announced at HUAWEI CONNECT 2026

Huawei's September 17 keynote focused heavily on the infrastructure needed for what the company calls the “agentic world.”

The company introduced an 11-chip portfolio designed for SuperPoDs and SuperClusters. The Ascend family sits at the center of that portfolio, while other components handle computing, interconnect, storage and management.

The current roadmap looks like this:

Chip	Planned availability	Intended direction
Ascend 960DT	Q1 2027	AI training
Ascend 960PR	Q3 2027	AI inference
Ascend 970	2028	Next-generation AI computing
Ascend 980	2029	Next-generation AI computing

Huawei says it is moving toward a one-generation-per-year cycle for the Ascend family. According to the company, the future chips are expected to increase compute specifications while also improving memory bandwidth, memory capacity and interconnect bandwidth. These are Huawei's roadmap targets rather than independently verified future benchmarks.

Why the Ascend 960DT launch acceleration matters

The biggest immediate change is timing.

Huawei previously had the Ascend 960 generation on a much later schedule. The company now says the 960DT will arrive in Q1 2027, while the 960PR follows in Q3.

That split also tells us something about how AI infrastructure is evolving.

Training and inference are related workloads, but they have different requirements. Training large models involves enormous datasets and repeated computation across many accelerators. Inference is about serving trained models to users and applications, often with different priorities around latency, throughput and operating cost.

By separating the 960 generation into training and inference variants, Huawei is signaling that it wants to optimize its hardware roadmap around these different workloads.

The company has not yet published a complete set of final specifications for both chips, so comparisons based on unverified numbers should be treated carefully.

Huawei is attacking the problem at the cluster level

This is perhaps the more interesting part of the announcement.

The traditional way of thinking about AI chips is simple: make each accelerator faster, add more memory and connect more accelerators together.

But once AI clusters become extremely large, communication between processors can become a serious bottleneck.

Huawei's answer is its SuperPoD architecture.

A SuperPoD tightly connects multiple computing nodes so that they can operate more like a single large machine. Huawei says its new architecture is designed to reduce communication overhead and allow large numbers of accelerators to work together more efficiently.

The company's 2026 presentation described systems capable of connecting thousands of AI accelerators.

That matters because a faster accelerator can still spend time waiting for data. If processors are constantly waiting for other processors, theoretical compute performance does not translate directly into useful AI performance.

This is why interconnect technology has become such a big part of the AI hardware market.

Near-Packaged Optics is one of Huawei's key bets

Huawei also highlighted Near-Packaged Optics, or NPO, in its new AI infrastructure.

The basic idea is straightforward.

As AI clusters grow, enormous amounts of data have to move between chips. Traditional electrical connections and conventional optical modules become increasingly difficult to scale because bandwidth, power consumption, physical density and reliability all become concerns.

NPO moves optical components closer to the computing hardware.

Huawei says its Hi-ONE optical technology can provide 7.2 Tbps of transmission capacity per unit. The company says the Atlas 960E SuperPoD can use thousands of these optical engines and reduce the number of conventional optical modules required by the system. Huawei also claims that the design can cut power consumption by more than 550 kW and improve system reliability.

Those figures are Huawei's own claims and should not be interpreted as independent benchmarks.

Still, the direction is significant.

AI infrastructure is becoming increasingly limited by the movement of data, not simply by the raw number of accelerator cores.

UnifiedBus is Huawei's attempt to connect the entire AI system

Huawei is also pushing UnifiedBus as a central part of its architecture.

Instead of treating processors, memory, storage and networking as separate components connected through several layers, Huawei wants a more tightly integrated system.

The company's latest portfolio uses UnifiedBus to connect components across its SuperPoD and SuperCluster architecture. Huawei says this approach is intended to improve communication between computing resources and reduce the overhead associated with moving data through large AI systems.

This is a crucial area of competition.

AI infrastructure companies are no longer competing only on accelerator performance. They are also competing on:

• Memory bandwidth
• Interconnect speed
• Network architecture
• Power efficiency
• Software compatibility
• Cluster management
• Storage performance
• Reliability at scale

That broader systems approach is becoming increasingly important as models grow.

Huawei says demand is already bigger than supply

There is another interesting detail behind the roadmap.

Huawei executives said demand for the company's AI computing equipment in China currently exceeds its production capacity.

Reuters reported that rotating chairman Eric Xu said Huawei cannot currently produce enough AI computing equipment to satisfy domestic demand, which limits the company's ability to expand internationally.

That creates an unusual situation.

Huawei is accelerating its product roadmap while simultaneously facing supply constraints.

The company therefore has two separate challenges: developing competitive hardware and producing enough of it at scale.

AI infrastructure requires much more than an accelerator chip. It requires advanced packaging, memory, networking equipment, power systems, cooling and manufacturing capacity. Shortages in any one part of that chain can limit the number of complete systems that can actually be deployed.

The software question remains just as important

Hardware is only one half of the AI accelerator battle.

Nvidia's position in AI computing has been strengthened by CUDA, its mature software ecosystem and years of developer adoption.

Huawei is trying to build a broader software ecosystem around Ascend. The company says it will continue opening parts of its software stack and supporting a wide range of models and applications.

That could become one of the biggest factors determining how widely Ascend systems are adopted.

Developers do not want to rewrite every AI application for a different accelerator.

They want frameworks, libraries, compilers, debugging tools and deployment systems that work with minimal friction.

Hardware specifications can change quickly. Software ecosystems generally take much longer to build.

Huawei's one-million-processor vision

Huawei is also thinking beyond individual SuperPoDs.

The company has described a Peerium architecture designed to connect very large numbers of processors. Reuters reported that Huawei is targeting systems capable of linking up to one million processors.

That does not mean Huawei currently operates a one-million-processor AI system at that scale.

It is an architectural target.

The distinction is important because connecting thousands or millions of processors efficiently is an extremely difficult engineering problem. Communication overhead, synchronization, memory access, cooling, power delivery and fault tolerance all become more complicated as a cluster grows.

Huawei's approach is essentially to make the entire AI infrastructure behave more like one giant computing system.

Why this matters beyond Huawei

The significance of the announcement extends beyond one company's chip roadmap.

AI companies are demanding larger clusters because newer models require more computation. At the same time, data centers are facing limits around electricity, cooling, networking and physical space.

That is pushing chip designers to think about the entire computing stack.

The next wave of AI infrastructure is therefore likely to involve several technologies working together:

Technology	Why it matters
AI accelerators	Provide the raw compute needed for training and inference
HBM	Feeds accelerators with large volumes of data
High-speed interconnects	Allow accelerators to communicate efficiently
Optical networking	Helps scale bandwidth while managing power and density
System architecture	Combines thousands of components into usable computing platforms
Software stack	Lets developers actually use the hardware efficiently

The companies that solve all of these problems together will have an advantage in building large AI infrastructure.

What developers and businesses should watch

For developers, the immediate impact of Huawei's announcement is unlikely to be about buying an Ascend 960 tomorrow. These chips are still on the roadmap.

The more important trend is the rapid specialization of AI infrastructure.

Training hardware is being optimized differently from inference hardware. Networking is becoming part of the accelerator architecture. Optical communication is moving closer to processors. Software frameworks are increasingly being designed to support multiple accelerator platforms.

Businesses evaluating AI infrastructure should therefore look beyond peak FLOPS.

A more useful checklist includes:

• Real-world inference performance
• Training efficiency
• Memory capacity and bandwidth
• Interconnect performance
• Power consumption
• Software compatibility
• Availability of developer tools
• Supply and deployment capacity
• Long-term maintenance support

The AI chip race is becoming a systems race

Huawei's latest announcement makes one thing clear: the AI hardware competition is no longer just about producing a faster chip.

The company is building a complete infrastructure strategy around Ascend accelerators, SuperPoDs, UnifiedBus, optical connectivity and software.

The accelerated Ascend 960DT schedule gives Huawei a nearer-term product milestone, while the 970 and 980 roadmap shows where the company wants to go over the next several years.

Whether those plans translate into widespread deployments will depend on factors that cannot be determined from a product roadmap alone, including manufacturing capacity, software maturity, performance in real workloads and access to the components required for large-scale systems.

But the direction is unmistakable.

As AI models continue getting larger and AI agents run longer workloads, the bottleneck may increasingly move from the processor itself to everything connecting the processor to the rest of the machine.

And that could make the architecture around the AI chip just as important as the chip.